1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
[
{
"ArchStdEvent": "L3D_CACHE",
"BriefDescription": "This event counts operations that cause a cache access to the L3 cache, as defined by the sum of L2D_CACHE_REFILL_L3D_CACHE and L2D_CACHE_WB_VICTIM_CLEAN events."
},
{
"ArchStdEvent": "L3D_CACHE_RD",
"BriefDescription": "This event counts access counted by L3D_CACHE that is a Memory-read operation, as defined by the L2D_CACHE_REFILL_L3D_CACHE events."
},
{
"EventCode": "0x0390",
"EventName": "L2D_CACHE_REFILL_L3D_CACHE",
"BriefDescription": "This event counts operations that cause a cache access to the L3 cache."
},
{
"EventCode": "0x0391",
"EventName": "L2D_CACHE_REFILL_L3D_CACHE_DM",
"BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_CACHE caused by demand access."
},
{
"EventCode": "0x0392",
"EventName": "L2D_CACHE_REFILL_L3D_CACHE_DM_RD",
"BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_CACHE caused by demand read access."
},
{
"EventCode": "0x0393",
"EventName": "L2D_CACHE_REFILL_L3D_CACHE_DM_WR",
"BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_CACHE caused by demand write access."
},
{
"EventCode": "0x0394",
"EventName": "L2D_CACHE_REFILL_L3D_CACHE_PRF",
"BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_CACHE caused by prefetch access."
},
{
"EventCode": "0x0395",
"EventName": "L2D_CACHE_REFILL_L3D_CACHE_HWPRF",
"BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_CACHE caused by hardware prefetch access."
},
{
"EventCode": "0x0396",
"EventName": "L2D_CACHE_REFILL_L3D_MISS",
"BriefDescription": "This event counts operations that cause a miss of the L3 cache."
},
{
"EventCode": "0x0397",
"EventName": "L2D_CACHE_REFILL_L3D_MISS_DM",
"BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_MISS caused by demand access."
},
{
"EventCode": "0x0398",
"EventName": "L2D_CACHE_REFILL_L3D_MISS_DM_RD",
"BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_MISS caused by demand read access."
},
{
"EventCode": "0x0399",
"EventName": "L2D_CACHE_REFILL_L3D_MISS_DM_WR",
"BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_MISS caused by demand write access."
},
{
"EventCode": "0x039A",
"EventName": "L2D_CACHE_REFILL_L3D_MISS_PRF",
"BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_MISS caused by prefetch access."
},
{
"EventCode": "0x039B",
"EventName": "L2D_CACHE_REFILL_L3D_MISS_HWPRF",
"BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_MISS caused by hardware prefetch access."
},
{
"EventCode": "0x039C",
"EventName": "L2D_CACHE_REFILL_L3D_HIT",
"BriefDescription": "This event counts operations that cause a hit of the L3 cache."
},
{
"EventCode": "0x039D",
"EventName": "L2D_CACHE_REFILL_L3D_HIT_DM",
"BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_HIT caused by demand access."
},
{
"EventCode": "0x039E",
"EventName": "L2D_CACHE_REFILL_L3D_HIT_DM_RD",
"BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_HIT caused by demand read access."
},
{
"EventCode": "0x039F",
"EventName": "L2D_CACHE_REFILL_L3D_HIT_DM_WR",
"BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_HIT caused by demand write access."
},
{
"EventCode": "0x03A0",
"EventName": "L2D_CACHE_REFILL_L3D_HIT_PRF",
"BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_HIT caused by prefetch access."
},
{
"EventCode": "0x03A1",
"EventName": "L2D_CACHE_REFILL_L3D_HIT_HWPRF",
"BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_HIT caused by hardware prefetch access."
},
{
"EventCode": "0x03A2",
"EventName": "L2D_CACHE_REFILL_L3D_MISS_PFTGT_HIT",
"BriefDescription": "This event counts the number of L3 cache misses where the requests hit the PFTGT buffer."
},
{
"EventCode": "0x03A3",
"EventName": "L2D_CACHE_REFILL_L3D_MISS_PFTGT_HIT_DM",
"BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_MISS_PFTGT_HIT caused by demand access."
},
{
"EventCode": "0x03A4",
"EventName": "L2D_CACHE_REFILL_L3D_MISS_PFTGT_HIT_DM_RD",
"BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_MISS_PFTGT_HIT caused by demand read access."
},
{
"EventCode": "0x03A5",
"EventName": "L2D_CACHE_REFILL_L3D_MISS_PFTGT_HIT_DM_WR",
"BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_MISS_PFTGT_HIT caused by demand write access."
},
{
"EventCode": "0x03A6",
"EventName": "L2D_CACHE_REFILL_L3D_MISS_L_MEM",
"BriefDescription": "This event counts the number of L3 cache misses where the requests access the memory in the same socket as the requests."
},
{
"EventCode": "0x03A7",
"EventName": "L2D_CACHE_REFILL_L3D_MISS_FR_MEM",
"BriefDescription": "This event counts the number of L3 cache misses where the requests access the memory in the different socket from the requests."
},
{
"EventCode": "0x03A8",
"EventName": "L2D_CACHE_REFILL_L3D_MISS_L_L2",
"BriefDescription": "This event counts the number of L3 cache misses where the requests access the different L2 cache from the requests in the same Numa nodes as the requests."
},
{
"EventCode": "0x03A9",
"EventName": "L2D_CACHE_REFILL_L3D_MISS_NR_L2",
"BriefDescription": "This event counts the number of L3 cache misses where the requests access L2 cache in the different Numa nodes from the requests in the same socket as the requests."
},
{
"EventCode": "0x03AA",
"EventName": "L2D_CACHE_REFILL_L3D_MISS_NR_L3",
"BriefDescription": "This event counts the number of L3 cache misses where the requests access L3 cache in the different Numa nodes from the requests in the same socket as the requests."
},
{
"EventCode": "0x03AB",
"EventName": "L2D_CACHE_REFILL_L3D_MISS_FR_L2",
"BriefDescription": "This event counts the number of L3 cache misses where the requests access L2 cache in the different socket from the requests."
},
{
"EventCode": "0x03AC",
"EventName": "L2D_CACHE_REFILL_L3D_MISS_FR_L3",
"BriefDescription": "This event counts the number of L3 cache misses where the requests access L3 cache in the different socket from the requests."
},
{
"ArchStdEvent": "L3D_CACHE_LMISS_RD",
"BriefDescription": "This event counts access counted by L3D_CACHE that is not completed by the L3D cache, and a Memory-read operation, as defined by the L2D_CACHE_REFILL_L3D_MISS events."
}
]