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[
{
"ArchStdEvent": "L3D_CACHE_ALLOCATE",
"PublicDescription": "Counts level 3 cache line allocates that do not fetch data from outside the level 3 data or unified cache. For example, allocates due to streaming stores."
},
{
"ArchStdEvent": "L3D_CACHE_REFILL",
"PublicDescription": "Counts level 3 accesses that receive data from outside the L3 cache."
},
{
"ArchStdEvent": "L3D_CACHE",
"PublicDescription": "Counts level 3 cache accesses. Level 3 cache is a unified cache for data and instruction accesses. Accesses are for misses in the lower level caches or translation resolutions due to accesses."
},
{
"ArchStdEvent": "L3D_CACHE_RD",
"PublicDescription": "Counts level 3 cache accesses caused by any memory read operation. Level 3 cache is a unified cache for data and instruction accesses. Accesses are for misses in the lower level caches or translation resolutions due to accesses."
},
{
"ArchStdEvent": "L3D_CACHE_LMISS_RD",
"PublicDescription": "Counts any cache line refill into the level 3 cache from memory read operations that incurred additional latency."
},
{
"ArchStdEvent": "L3D_CACHE_MISS",
"PublicDescription": "Counts level 3 cache accesses that missed in the level 3 cache."
}
]